The present invention is directed to a semiconductor device and the method thereof, and more particularly to an interconnection structure in a semiconductor device and the method thereof which allows a thin lower conductive layer and an upper conductive layer to make ohmic contact.
In the pursuit of semiconductor device miniaturization from VLSI to ULSI, many problems concerning interconnections need to be solved. They are caused by the geometrical increment of levels, the miniaturization of contact holes and via holes, limitations on the coating of conductive material, and poor connections due to the thinness of the device.
FIG. 1 shows a vertical sectional view of a conventional semiconductor device having a contact hole for connecting upper and lower conductive layers. The semiconductor device comprises an electrically insulated substrate 1 on the surface of which a thick insulating layer 2 is formed, a first conductive layer 3 deposited and patterned on the insulating layer, for instance to a thickness of about 3000 to 4000.sup..ANG., a thick insulating layer 4 formed on the insulating and first conductive layers, a contact hole 5 for partially exposing the first conductive layer 3, and for interconnecting a layer of metallization 6 and the first conductive layer 3, and the layer of metallization 6 formed on the partially exposed first conductive layer and the insulating layer 4.
The contact hole 5 for interconnecting the first conductive layer 3 and the layer of metallization 6 plays the role of sending information of the first conductive layer to the layer of metallization and vice versa. The reliability of the information transfer depends not only upon the properties of the conductive layer itself but also the contact between the conductive layers.
In FIG. 1 the contact hole 5 is formed by anisotropic etching, for example reactive ion etching (RIE), which simplifies highly dense integration of the circuit.
The miniaturization of integrated circuitly by the high density of the devices requires to contract not only the overall size of the device, but also selectively its width and/or thickness. For example, in a static RAM, a polysilicon layer is partially thinned to form a highresistance unit in each memory cell or, instead of the thinned highly resistant poly silicon layer, a thin PMOS transistor (TFT SRAM) is introduced.
FIG. 2 is a vertical sectional view of a semiconductor device of a general interconnection structure having a thin conductive layer and depicts the same process as FIG. 1 except that where the thickness of the first conductive layer of FIG. 1 is about 3000 to 4000.sup..ANG., in FIG. 2 it is thinned to about 500.sup..ANG..
Accordingly, an insulating level 4 is provided on a substrate 1 on which a thin conductive layer 7 has been formed on an insulating layer 2. Thereafter, a contact hole 5 is formed by anisotropic etching, e.g., an RIE method so that part of the thin conductive layer 7 is exposed. Then, conductive material is deposited and patterned on the surface of the insulating layer 4 and the exposed thin conductive layer, which completes the general interconnection structure including the thin conductive layer 7, the contact hole 5 and the layer of metallization 6.
When the contact hole 5 is formed by anisotropic etching, e.g., RIE, the etch selectivity of the thin conductive layer 7, e.g., an impurity-doped polysilicon layer against the insulating layer 4 to be processed is not so high (generally below 10). Therefore, when the first conductive layer 7 is formed very thin, i.e., to a thickness of about 500.sup..ANG., as mentioned above, if a part of the insulating layer 4 is etched one and a half times as long as the conventional one which is an allowable error or processing margin, or if the layer is etched by a much lower etch selectivity, the insulating layer 4 together with the thin conductive layer 7 and even a part of the insulating layer 2 are etched by the above mentioned etching method, thereby partially exposing the semiconductor substrate 1. If the layer of metallization 6 is formed under these conditions, the layer of metallization is directly connected to the exposed portion of the substrate 1, causing a poor interconnection.
Further, even if the insulating layer 2 is left intact, the whole exposed surface of the thin conductive layer and the layer of metallization to be connected are connected only to the exposed edges of the thin conductive layer 7, part of which is removed by the etching process, which substantially diminishes the contact area to worsen the resistive contact.
FIG. 3 is a vertical sectional view of a conventional interconnection structure introducing a method in which the thin conductive layer and the layer of metallization are indirectly connected via an interposing conductive material such as metal, silicide or a thick polysilicon layer.
The conventional semiconductor device comprises a semiconductor substrate 1 electrically isolated by forming a thick insulating layer 2 thereon, a third conductive layer 8 patterned on the insulating layer, a thin conductive layer 7 isolated from the third conductive layer 8 by the first interlaid insulating layer 9 and connected to the third conductive layer 8 through the first contact hole 100, and a metallization 6 which is isolated from the third conductive layer 8 by the first and second interlaid insulating layers 9 and 10 and isolated from the thin conductive layer 7 by the second interlaid isolating layer 10 only, is connected to the third conductive layer 8 through the second contact hole 200.
According to the conventional method, as thin conductive layer 7 is connected to the third conductive layer 8 through first contact hole 100 first, and the third conductive layer 8 is again connected to a metallization 6 through the second contact hole 200, information applied to the thin conductive layer 7 is transferred to the metallization 6 through the third conductive layer 8, and vice versa.
This prevents poor ohmic contacts due to reduction of connecting surface area since the thin conductive layer is connected to the metallization without directly forming the contact hole connecting the metallization layer on the thin conductive layer. However, metal, silicide or polysilicon layer used as the third conductive layer still has a problem.
When using metal or silicide, the type of contact for interconnecting the thin and third conductive layers is determined by the type of impurities-doped polysilicon used as the thin conductive layer, and a ohmic contact is available for N-type impurities. P-type impurities create the same effect as a PN junction between the thin and third conductive layers, causing a rectified contact which makes for a poor contact.
Also, when using thick polysilicon as the third conductive layer, the type of impurities doped in the thick polysilicon layer is determined according to the impurity type of impurity-doped polysilicon used as the thin conductive layer. It is desirable that the types of the two impurities are the same for a highly reliable ohmic contact.
The interconnection of the conventional semiconductor device prevents removing the thin conductive layer by overetching, but, since information is transmitted through a third conductive layer, it causes a poor contact due to the difference in the properties between the third conductive layer and the adjacent material.